View TDA9950_4664754.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA9950
CEC/I2C-bus translator
Rev. 02 -- 22 October 2009 Product data sheet
1. General description
The TDA9950 is a single-chip CEC/I2C-bus translator with a processor, dedicated to the control and interfacing of the Consumer Electronics Control (CEC), a feature of the High-Definition Multimedia Interface (HDMI). The TDA9950 is an interface between the CEC protocol and timings and the standard I2C-bus. A message received on the I2C-bus interface is written in a buffer and sent on the CEC line. A message received from the CEC line is stored in a buffer, and an interrupt is generated indicating that a message can be read via the I2C-bus. To reduce its power consumption the TDA9950 sets itself to Idle mode when there is no message on the CEC line nor on the I2C-bus.
2. Features
2.1 Principal features
I I I I I I I I Receive and transmit CEC messages with compliant Signal Free Time handling I2C-bus interface to host supporting 100 kbit/s and 400 kbit/s communication Supports multiple CEC logical addresses Supports CEC messages up to 16 bytes in length Programmable retry count Comprehensive arbitration and collision handling 3.0 V to 3.6 V VDD operating range Automatic Idle mode to reduce power consumption when there is no message on CEC line and I2C-bus I I/O pins are 5 V tolerant
2.2 Additional features
I Processor with embedded software to control the interface between CEC line and I2C-bus I Active-LOW reset input and on-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. I On-chip oscillator for 12 MHz crystal I Schmitt trigger port inputs
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
3. Applications
I I I I I I I All devices using an HDMI connector YCBCR or RGB high-speed video digitizer Projector, plasma and LCD TV Rear-projection TV High-end TV Home-theater amplifier DVD recorder
4. Quick reference data
Table 1. Symbol VDD Tamb Ptot Quick reference data Parameter supply voltage ambient temperature total power dissipation Operating mode Idle mode I2C-bus: (5 V tolerant) pins SDA and SCL fclk clock frequency Standard mode Fast mode 100 400 kHz kHz Conditions Min 3.0 0 Typ 3.3 33 16 Max 3.6 70 46.8 25.2 Unit V C mW mW
5. Ordering information
Table 2. Ordering information Package Name TDA9950TT TSSOP20 Description plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT360-1 Type number
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
2 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
6. Block diagram
TDA9950
CEC_IN CEC-BUS CEC_OUT internal bus DATA RAM
CPU A0 A1 SCL SDA
I2C-BUS
INTERRUPT
INT INT_POL
XTAL1 CRYSTAL XTAL2 CONFIGURABLE OSCILLATOR POWER-ON RESET RST
001aag922
Fig 1.
Block diagram
7. Pinning information
7.1 Pinning
RSVD1 INT CEC_OUT RST VSS XTAL1 XTAL2 CEC_IN SDA
1 2 3 4 5 6 7 8 9
20 A0 19 A1 18 INT_POL 17 RSVD7 16 RSVD6 15 VDD 14 RSVD5 13 RSVD4 12 RSVD3 11 RSVD2
001aag923
TDA9950
SCL 10
Fig 2.
Pin configuration
7.2 Pin description
Table 3. Symbol RSVD1 INT Pin description Pin 1 2 Type[1] I O Description RSVD1 -- Reserved pin; shall be connected to ground INT -- Interrupt line to the host processor to indicate data is available for reading. The polarity of this signal depends on the state of pin INT_POL. CEC_OUT -- Output for CEC line (open-drain).
CEC_OUT
3
O
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
3 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
Pin description ...continued Pin 4 5 6 7 8 9 10 11 12 13 14 15 Type[1] I P I O I I/O I I O O I P Description RST -- External reset input. A LOW state on this pin resets the translator. Ground: 0 V reference (GND). XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (12 MHz crystal). XTAL2 -- Output from the oscillator amplifier. CEC_IN -- Input for CEC line. SDA -- I2C-bus serial data input/output (open-drain). SCL -- I2C-bus serial clock input. RSVD2 -- Reserved pin (should be connected to ground). RSVD3 -- Reserved pin. RSVD4 -- Reserved pin. RSVD5 -- Reserved pin (should be connected to ground). Power supply -- This is the (core digital 3.3 V) power supply voltage for normal operation as well as Idle and Power-down modes. RSVD6 -- Reserved pin (should be connected to ground). RSVD7 -- Reserved pin (should be connected to ground). INT_POL -- Sets the polarity of the active output required on the INT signal (pin 2). Leave floating or pull-up to VDD for a HIGH output when active (rising edge), connect to VSS for a LOW output when active (falling edge). This input is latched at reset. A1 -- I2C-bus slave address bit 2. A0 -- I2C-bus slave address bit 1.
Table 3. Symbol RST VSS XTAL1 XTAL2 CEC_IN SDA SCL RSVD2 RSVD3 RSVD4 RSVD5 VDD
RSVD6 RSVD7 INT_POL
16 17 18
I I I
A1 A0
[1]
19 20
I I
I = input, O = output, P = power supply.
8. Functional description
The TDA9950 uses an internal processor with embedded software to control the interface between the CEC line and the I2C-bus.
8.1 Device addressing
The TDA9950 is a slave I2C-bus device and the SCL pin is an input pin only. The timing and protocol for the I2C-bus are standard.
Table 4. Bit Value
[1]
Device address code Device code b7[1] 0 b6 1 b5 1 b4 0 b3 1 Chip enable b2 A1 b1 A0 R/W b0 R/W
Address code
The Most Significant Bit (MSB), b7, is sent first.
A1 and A0 are hardware-selectable pins.
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
4 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
In case of independent CEC, a system could have up to four TDA9950 devices on the same I2C-bus. The four addresses are defined by the state of the inputs A0 and A1 (logic 1 when connected to VDD, logic 0 when connected to GND).
8.2 Configuring the TDA9950
The TDA9950 is controlled via a series of registers.
Table 5. Register APR CSR CER CVR CCR ACKH ACKL CCONR CDR I2C-bus register configuration Description Address Pointer Register TDA9950 Status Register TDA9950 Error Register TDA9950 Version Register TDA9950 Control Register CEC Address ACK High register CEC Address ACK Low register CEC Configuration Register CEC Data Registers Address 00h 00h 01h 02h 03h 04h 05h 06h 07h - 19h Read/Write W R R R R/W R/W R/W R/W R/W
The first byte of any I2C-bus write frame configures the address pointer register APR, which determines the first TDA9950 register that will be read or written in the remainder of the I2C-bus transfer. If a read is carried out without a prior write to the address pointer register, the register returned will be that to which the address pointer register was last set. The address pointer auto-increments after a successful read or write for all address pointer values other than 00h. Auto-incremented addresses above 19h are invalid and ignored. Registers 01h to 06h are used for configuration of the TDA9950, whilst repeated auto-incremented reads starting at register 07h are used to transfer CEC data. Setting the address pointer register higher than 07h is treated as setting it to 07h, as all message data transfers must start from register 07h and continue by auto-incrementing in one contiguous transfer. Transfers via the data registers are formatted using the data register protocol described in Section 8.5.
8.3 Use of the INT line
As the TDA9950 is an I2C-bus slave device, it provides an additional I/O line to signal to the host that data is available for reading. This is the INT output line, which should be monitored by the host. An additional TDA9950 input, on pin INT_POL, allows configuration of the polarity of operation of the INT line. When the INT line is active, it will match the state of the input on pin INT_POL. The state of the INT line is always reflected in the TDA9950 Status Register, so it is possible to regularly poll this register instead of monitoring the INT line. However, this method is less efficient and not recommended. The INT indication in the TDA9950 Status Register is not affected by the setting of the INT polarity input on pin INT_POL.
TDA9950_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
5 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
8.4 Register descriptions
Table 6. Bit 7 to 5 4 to 0 APR - Address Pointer Register (address 00h) bit description (Write mode) Symbol reserved REG_PTR[4:0] Description reserved (must be set to 000) Address Pointer: Address of the register that will be read/written during further I2C-bus communication.
Table 7. Bit 7
CSR - TDA9950 Status Register (address 00h) bit description (Read mode) Symbol BUSY Description BUSY: 0 = the TDA9950 is able to handle requests. 1 = the TDA9950 is busy and cannot accept any further request.
6
INT
INT: 0 = the INT interrupt output is inactive. 1 = the INT interrupt output is active.
5
ERR
ERR: 0 = no error. 1 = an error occurred (specified in the TDA9950 Error Register). Cleared by a read of the TDA9950 Error Register.
4 to 0 Table 8. Bit 7 to 0
-
not used CER - TDA9950 Error Register (address 01h) bit description (Read only)
Symbol CER[7:0]
Description TDA9950 Error Register: This register provides details of the last error that occurred. Reading this register resets the ERR bit in the TDA9950 Status Register. 00h = no error has occurred since reset. 01h = watchdog reset has occurred. 02h = long CEC message with no End Of Message (EOM) detected. 03h = CEC overrun - no buffer available to receive.
Table 9. Bit 7 to 4 3 to 0
CVR - TDA9950 Version Register (address 02h) bit description (Read only) Symbol CVR_MAJ[3:0] CVR_MIN[3:0] Description TDA9950 major version register: Major version TDA9950 minor version register: Minor version
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
6 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
CCR - TDA9950 Control Register (address 03h) bit description (Read/Write) Symbol RESET Description RESET: Resets the TDA9950. Any transmission in progress will be completed first - the reset occurs once the TDA9950 returns to the idle state. All default values will be restored. 0 = no specific action. 1 = resets the TDA9950.
Table 10. Bit 7
6
ON_OFF
ON_OFF: 0 = the TDA9950 is disabled (after completion of any pending CEC transmission or reception) and will no longer acknowledge any message on the CEC line or accept any message for transmission. 1 = the TDA9950 is enabled and will acknowledge messages according to the logical address bits in the CEC Address ACK High and CEC Address ACK Low registers.
5 to 0 Table 11. Bit 7 6 to 0
-
not used ACKH - CEC Address ACK High register (address 04h) bit description (Read/Write)
Symbol reserved ACKH[6:0]
Description reserved (must be set to 0) CEC Address ACK High register For each bit: 0 = messages to the corresponding logical address will not be acknowledged. 1 = messages to the corresponding logical address are acknowledged and forwarded to the host.
Table 12. Bit 7 to 0
ACKL - CEC Address ACK Low register (address 05h) bit description (Read/Write) Symbol ACKL[7:0] Description CEC Address ACK Low register For each bit: 0 = messages to the corresponding logical address will not be acknowledged. 1 = messages to the corresponding logical address are acknowledged and forwarded to the host.
Table 13. Bit 7 to 5 -
CCONR - CEC Configuration Register (address 06h) bit description (Read/Write) Symbol Description not used
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
7 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
CCONR - CEC Configuration Register (address 06h) bit description (Read/Write) Symbol ENABLE_ERROR Description ENABLE_ERROR: 0 = no specific action. 1 = notify the host of all errors via the TDA9950 Error Register and via the CECData.err service (see Section 8.5.4).
Table 13. Bit 4
3 2 to 0
RETRY[2:0]
not used RETRY[2:0]: retry count to be used by the TDA9950. The maximum value is 5; values greater than 5 will still give 5 retries.
Table 14. Bit 7 to 0
CDR[0:18] - CEC Data Registers (addresses 07h to 19h) bit description (Read/Write) Symbol FrameByteCount/ ServiceSelector/ Parameters[7:0] Description FrameByteCount/ServiceSelector/Parameters: Length of message in B, Type of message, 17 B for message content; see Section 8.5 "Data register protocol".
8.5 Data register protocol
Communication between the TDA9950 and the host using the CEC Data Registers is carried out using frames of information. The host is the master of all data transfers; the TDA9950 uses the INT line to inform the host that it has data available. Before a frame is read or written, the host must set the REG_PTR field in the Address Pointer Register to the base CEC Data Register address. Successive reads or writes automatically increment the REG_PTR as the frame is transferred. Message transfers can only start from the first CEC Data Register at address 07h and not from higher addresses, as messages must be transferred complete and not in fragments. Each frame consists of a byte count, a service selector and then zero or more (up to 17) parameters as shown in Figure 3.
Register CDR0 FrameByteCount
Register CDR1 ServiceSelector
Register CDR2
[...]
[...]
[Parameters]
001aag924
Fig 3.
Frame format for the data register protocol
The FrameByteCount indicates the number of bytes in the frame (including the FrameByteCount itself). The service is specified by the ServiceSelector (see Table 15). The remaining bytes of the frame, if any, contain the parameters associated with a particular service. The maximum length of a frame is 19 bytes. The TDA9950 will only accept a single outstanding request. Reading message bytes beyond FrameByteCount will return FFh. Table 15 shows the organization of the ServiceSelector values. If an unused ServiceSelector is sent to the TDA9950 it will respond with the confirmation Bad .req service (see Table 17). For every service, the parameters that are defined in the following sections are mandatory. No service contains optional parameters.
TDA9950_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
8 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
CEC Data services From host to TDA9950 CECData.req CECData.cnf CECData.ind (indication, no TDA9950 error) CECData.err (no indication, TDA9950 error) CECData.ier (indication, TDA9950 error) From TDA9950 to host Section 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5
Table 15. 00h 01h 81h 82h 83h
ServiceSelector
8.5.1 CECData.req service
This service is used to transfer CEC message data. The parameters for the service are shown in Table 16. Transmission of the CEC message commences as soon as the complete message has been received by the TDA9950 (subject to the appropriate Signal Free Time rules being satisfied).
Table 16. Parameter AddressByte DataBytes Parameters for CECData.req service Comments Source and destination logical addresses in the form SSSS DDDD Bytes of message data up to the data length indicated by FrameByteCount
8.5.2 CECData.cnf service
This service is used by the TDA9950 to inform the host of the success or other result of a CECData.req service. The parameters are shown in Table 17.
Table 17. Parameter ResultCode Parameters for CECData.cnf service Comments Value Meaning Success TDA9950 in off state Bad .req service Failed, unable to access CEC line Failed, arbitration error Failed, bit timing error Failed, destination address not acknowledged Failed, data byte not acknowledged A value indicating the result 00h of the transmission 80h 81h 82h 83h 84h 85h 86h
8.5.3 CECData.ind service
This service is used to transfer a CEC message, received from a remote device, to the host. The parameters are listed in Table 18.
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
9 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
Parameters for CECData.ind service Comments Source and destination logical addresses in the form SSSS DDDD Bytes of message data up to the data length indicated by FrameByteCount
Table 18. Parameter
AddressByte DataBytes
8.5.4 CECData.err service
This service is used to alert the host to an error condition. There are no parameters. The host should read the TDA9950 Error Register CER for details of the error. This indication will only occur when bit ENABLE_ERROR of the CEC Configuration Register CCONR is set to enable error indications.
8.5.5 CECData.ier service
This service is used to transfer a CEC message, received from a remote device, to the host. In addition, it also alerts the host to an error condition. The parameters are listed in Table 19. The host should read the TDA9950 Error Register CER for details of the error. This indication will only occur when bit ENABLE_ERROR of the CEC Configuration Register CCONR is set to enable error indications. This service will not be used if no such errors are implemented.
Table 19. Parameter AddressByte DataBytes Parameters for CECData.ier service Comments Source and destination logical addresses in the form SSSS DDDD Bytes of message data up to the data length indicated by FrameByteCount
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
10 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
8.6 Example communication sequences
When writing, the first byte after the slave address will contain the Address Pointer Register value. Subsequent bytes are written to the register addressed by the Address Pointer Register. If the host wishes to write to two or more discontiguous registers, two separate write sequences must be used with a STOP/START or repeated START condition between them. Contiguous ranges of registers can be written in one communication sequence between a START and STOP condition. Messages in the CEC Data Registers must be written and read as contiguous ranges of registers. When reading, values are read starting at the register currently addressed by the Address Pointer Register. The pointer auto-increments after each read. If the host should read past register 19h, or read more bytes than indicated by the FrameByteCount in register CDR[0] (address 07h), the value FFh will be returned. When the address pointer is 00h, it does not auto-increment. This allows repetitive polling of the TDA9950 Status Register without the need to reset the Address Pointer Register. If the address pointer needs to be set before a read takes place, the host must first write to the Address Pointer Register and then, after a repeated start condition (or a STOP/START sequence), commence reading as many data bytes as it requires.
S
SLAVE ADDRESS
W
A
0000 0000
A
Sr
SLAVE ADDRESS
R
A

A
P
write address pointer '0' (write) Sr = repeated START condition
'1' (read)
read status
from master to slave
from slave to master
001aag925
A = acknowledge (SDA = LOW) S = START condition P = STOP condition
Fig 4.
Host reads TDA9950 Status Register - after setting address pointer
S
SLAVE ADDRESS
R
A

A
P
'1' (read)
read status
from master to slave
from slave to master
001aag926
A = acknowledge (SDA = LOW) S = START condition P = STOP condition
Fig 5.
Host reads TDA9950 Status Register - without setting address pointer (was at 0)
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
11 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
S
SLAVE ADDRESS
W
A
0000 0100
A
Sr
SLAVE ADDRESS
R
A

A
....

A
P
write address pointer '0' (write) Sr = repeated START condition
'1' (read) read address H
read address L
from master to slave
from slave to master
001aag927
A = acknowledge (SDA = LOW) S = START condition P = STOP condition R = read W = write
Fig 6.
Host reads CEC Address ACK registers - after setting address pointer
S
SLAVE ADDRESS
W
A
0000 0110
A

A
P
'0' (write) write address pointer
write config
from master to slave
from slave to master
001aag928
A = acknowledge (SDA = LOW) S = START condition P = STOP condition W = write
Fig 7.
Host writes CEC Configuration Register - after setting address pointer
.....

A

A

A
P
write data 17h write data 18h from master to slave
write data 19h
from slave to master
001aag929
A = acknowledge (SDA = LOW) A = not acknowledge (SDA = HIGH) P = STOP condition
Fig 8.
Host writes last three CEC Data Registers
8.6.1 Notes on writing the CEC Data Registers
* The CEC Data Registers should be written starting from the first CEC Data Register,
for the number of registers indicated by the contents of that first CEC Data Register, in one contiguous operation.
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
12 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
* The length of the message is given by the byte in the first CEC Data Register. This will
be at least 3 for the shortest message. A value less than 3 indicates an invalid message.
* If fewer CEC Data Registers are written than the number indicated by the first CEC
Data Register, the partial message will be ignored and no confirmation will be returned.
* If more CEC Data Registers are written than the number indicated by the first CEC
Data Register, the message will be processed as soon as the message's last CEC Data Register is written, and the extra bytes written will be ignored.
* If the highest CEC Data Register is written and more message bytes are indicated by
the first CEC Data Register, the message will be processed as soon as the highest CEC Data Register is written, and the extra bytes written will be ignored.
8.6.2 Notes on reading the CEC Data Registers
* The CEC Data Registers only contain a valid message when the INT line is set and
the INT bit in the TDA9950 Status Register is set.
* If CEC Data Registers are read when the INT line is not set, the first CEC Data
Register will contain 0, indicating that there are no bytes to read. Any further reads before a STOP condition will return the value FFh.
* The CEC Data Registers should be read starting from the first CEC Data Register, for
the number of registers indicated by that first CEC Data Register, in one contiguous operation.
* If the host writes CEC Data Registers and then begins reading without first resetting
the Address Pointer Register, reading will automatically commence from the first CEC Data Register.
* If reading stops before all indicated CEC Data Registers are read, the TDA9950 will
reset the INT line and the message is discarded by the TDA9950 and will not be available for reading again.
* If reading continues for more CEC Data Registers than are indicated by the first CEC
Data Register, the value FFh will be read. The INT line is reset when the last valid CEC Data Register for the current message is read.
8.7 Using the TDA9950
8.7.1 Initialization
After a reset, first configure the TDA9950 with its logical address or addresses (as required):
* I2C_WRITE: 04h, 00h, 08h
Set Address Pointer to 04h (ACKH), set ACKH to 00h, and set ACKL to 08h. The TDA9950 is now configured to acknowledge messages to the logical address 3 (Tuner 1 (see HDMI1.3a specification) or STB1 (see HDMI1.2a specification)). Then set the TDA9950 to the ON state (mandatory):
* I2C_WRITE: 03h, 40h
Set Address Pointer to 03h (CCR), set CCR to 40h.
TDA9950_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
13 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
The TDA9950 is now enabled. Messages addressed to logical address Tuner 1 (see HDMI1.3a specification) or STB1 (see HDMI1.2a specification) will be acknowledged and forwarded to the host processor.
8.7.2 Sending a CEC message
Example: the host processor of Playback Device 1 (see HDMI1.3a specification) or DVD1 (see HDMI1.2a specification) wishes to send the message to TV:
* I2C_WRITE: 00h; I2C_READ, I2C_READ, ....
Set Address Pointer to 00h (CSR), read TDA9950 Status Register - repeat read until TDA9950 is no longer busy (bit CSR[7] = 0).
* I2C_WRITE: 07h, 04h, 00h, 40h, 0Dh
Set Address Pointer to 07h (CEC Data Register 1), write CEC Data Registers. FrameByteCount = 4, ServiceSelector = CECData.req, AddressByte = DVD/TV, DataByte = .
* Wait for INT line to be asserted
When TDA9950 has a response, it will assert the INT line (the host could also poll bit CSR[6]).
* I2C_WRITE: 07h; I2C_READ: 03h, 01h, 00h
Set Address Pointer to 07h (Data Register 1), read CEC Data Registers. FrameByteCount = 3, ServiceSelector = CECData.cnf, ResultCode = Success.
8.7.3 Receiving a CEC message
Example: TV sends the message to Playback Device 1 (see HDMI1.3a specification) or DVD1 (see HDMI1.2a specification):
* INT line is asserted
The TDA9950 at Playback Device 1 (see HDMI1.3a specification) or DVD1 (see HDMI1.2a specification) has acknowledged the message from TV and it is now available for reading by the Playback Device 1 (see HDMI1.3a specification) or DVD1 (see HDMI1.2a specification) host processor.
* I2C_WRITE: 07h; I2C_READ: 04h, 81h, 04h, 83h
Set Address Pointer to 07h (Data Register 1), read CEC Data Registers. FrameByteCount = 4, ServiceSelector = CECData.ind, AddressByte = TV/DVD, DataByte = .
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
14 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
9. Limiting values
Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb Tstg IOH(I/O) IOL(I/O) II/O(tot)(max) Vxtal Vn
[1]
Parameter ambient temperature storage temperature HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total I/O current crystal voltage voltage on any other pin
Conditions
Min 0 -65
Max 70 +150 8 20 80 VDD + 0.5 +5.5
Unit C C mA mA mA V V
all I/O and output pins
-
on pins XTAL1, XTAL2 except pins XTAL1, XTAL2, VDD
-0.5
Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
15 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
10. Static characteristics
Table 21. Static characteristics VDD = 3.0 V to 3.6 V; Tamb = 0 C to +70 C for industrial application; unless otherwise specified. Symbol VDD IDD Parameter supply voltage supply current VDD = 3.6 V; fosc = 12 MHz Operating mode Idle mode dV/dt VPOR Vth(HL) Vth(LH) Vhys VIL VIH VOL rate of change of voltage power-on reset voltage negative-going threshold voltage positive-going threshold voltage hysteresis voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage except pins SCL, SDA except pins SCL, SDA pins RST, CEC_IN, SDA, SCL, RSVD2 pins SCL, SDA only pins SCL, SDA only VDD = 2.4 V to 3.6 V; pin CEC_OUT IOL = 20 mA IOL = 3.2 mA VOH HIGH-level output voltage VDD = 2.4 V to 3.6 V; pin CEC_OUT IOH = -3.2 mA IOH = -20 A Vxtal Vn Vtrip(bo) Ptot crystal voltage voltage on any other pin brownout trip voltage total power dissipation on pins XTAL1, XTAL2; with respect to VSS except pins XTAL1, XTAL2, VDD; with respect to VSS 2.4 V < VDD < 3.6 V Operating mode Idle mode Rpu(int)(RST_N) internal pull-up resistance on pin RST I2C-bus: (5 V tolerant) pins SDA and SCL Cin
[1] [2] [3]
[2] [2]
Conditions
Min 3.0 0.22VDD -0.5 0.7VDD
Typ[1] 3.3 10 5 0.4VDD 0.6VDD 0.2VDD -
Max 3.6 13 7 2 50 0.2 0.7VDD 0.3VDD 5.5
Unit V mA mA mV/s mV/s V V V V V V
rise rate of VDD fall rate of VDD
-
0.6 0.2
1.0 0.3
V V
VDD - 0.7 VDD - 0.3 -0.5 -0.5 2.40 10
VDD - 0.4 VDD - 0.2 33 16 -
+4.0 +5.5 2.70 46.8 25.2 30
V V V V V mW mW k
input capacitance
[3]
-
-
10
pF
Typical ratings are not guaranteed. The values listed are at room temperature and VDD = 3.3 V. See Section 9 "Limiting values" for steady state (non-transient) limits on IOL or IOH. If IOL / IOH exceeds the test condition, VOL / VOH may exceed the related specification. Pin capacitance is characterized but not tested.
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
16 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
11. Dynamic characteristics
Table 22. Dynamic characteristics (12 MHz) VDD = 3.0 V to 3.6 V; Tamb = 0 C to +70 C for industrial applications; fosc = 12 MHz (crystal); unless otherwise specified. Symbol Glitch filter tgr tsa I2C-bus: fclk glitch rejection time signal acceptance time (5 V tolerant) pins SDA and SCL clock frequency Standard mode Fast mode 100 400 kHz kHz pin RST any pin except RST pin RST any pin except RST 125 50 50 15 ns ns ns ns Parameter Conditions Min Typ Max Unit
12. Application information
SCL SDA INT CEC_IN
220 pF
10 9 2 8
I2C-bus
27 k 47 k
VDD
TDA9950
3 20 19 18 1 CEC_OUT (I2C address) A0 (I2C address) A1 (polarity) INT_POL RSVD1
18 k 100 k
220 pF
PMLL4148 CEC line BC817
configuration
220
001aag930
Fig 9.
Application diagram
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
17 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
13. Package outline
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT360-1 (TSSOP20)
TDA9950_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
18 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
14. Revision history
Table 23. Revision history Release date 20091022 Data sheet status Product data sheet Change notice Supersedes TDA9950_1 Document ID TDA9950_2 Modifications:
* * * * *
Figure 1 "Block diagram": removed pin name CEC_POL Figure 2 "Pin configuration": changed pin name CEC_POL by RSVD1 Table 3 "Pin description": changed pin name CEC_POL by RSVD1 Table 3 "Pin description": updated description pin CEC_OUT Figure 9 "Application diagram": changed pin name CEC_POL by RSVD1 Product data sheet -
TDA9950_1
20071116
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
19 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
20 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
17. Tables
1 2 2.1 2.2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4 Configuring the TDA9950 . . . . . . . . . . . . . . . . . 5 Use of the INT line . . . . . . . . . . . . . . . . . . . . . . 5 Register descriptions . . . . . . . . . . . . . . . . . . . . 6 Data register protocol . . . . . . . . . . . . . . . . . . . . 8 CECData.req service . . . . . . . . . . . . . . . . . . . . 9 CECData.cnf service . . . . . . . . . . . . . . . . . . . . 9 CECData.ind service . . . . . . . . . . . . . . . . . . . . 9 CECData.err service. . . . . . . . . . . . . . . . . . . . 10 CECData.ier service . . . . . . . . . . . . . . . . . . . . 10 Example communication sequences . . . . . . . 11 8.6.1 8.6.2 8.7 8.7.1 8.7.2 8.7.3 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 Notes on writing the CEC Data Registers . . . Notes on reading the CEC Data Registers . . Using the TDA9950 . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . Sending a CEC message. . . . . . . . . . . . . . . . Receiving a CEC message . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 13 13 14 14 15 16 17 17 18 19 20 20 20 20 20 20 21 21 22
18. Figures
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .3 Frame format for the data register protocol . . . . . .8 Host reads TDA9950 Status Register - after setting address pointer. . . . . . . . . . . . . . . . . . . . .11 Fig 5. Host reads TDA9950 Status Register without setting address pointer (was at 0) . . . . . .11 Fig 6. Host reads CEC Address ACK registers after setting address pointer . . . . . . . . . . . . . . . .12 Fig 7. Host writes CEC Configuration Register after setting address pointer . . . . . . . . . . . . . . . .12 Fig 8. Host writes last three CEC Data Registers . . . . .12 Fig 9. Application diagram . . . . . . . . . . . . . . . . . . . . . . .17 Fig 10. Package outline SOT360-1 (TSSOP20). . . . . . . .18 Fig 1. Fig 2. Fig 3. Fig 4.
TDA9950_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 22 October 2009
21 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
19. Contents
1 2 2.1 2.2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.7 8.7.1 8.7.2 8.7.3 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4 Configuring the TDA9950 . . . . . . . . . . . . . . . . . 5 Use of the INT line . . . . . . . . . . . . . . . . . . . . . . 5 Register descriptions . . . . . . . . . . . . . . . . . . . . 6 Data register protocol . . . . . . . . . . . . . . . . . . . . 8 CECData.req service . . . . . . . . . . . . . . . . . . . . 9 CECData.cnf service . . . . . . . . . . . . . . . . . . . . 9 CECData.ind service . . . . . . . . . . . . . . . . . . . . 9 CECData.err service. . . . . . . . . . . . . . . . . . . . 10 CECData.ier service . . . . . . . . . . . . . . . . . . . . 10 Example communication sequences . . . . . . . 11 Notes on writing the CEC Data Registers. . . . 12 Notes on reading the CEC Data Registers . . . 13 Using the TDA9950 . . . . . . . . . . . . . . . . . . . . 13 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sending a CEC message . . . . . . . . . . . . . . . . 14 Receiving a CEC message. . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Static characteristics. . . . . . . . . . . . . . . . . . . . 16 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 Application information. . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 October 2009 Document identifier: TDA9950_2

▲Up To Search▲

Price & Availability of TDA9950

	To Download TDA9950 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .